This invention relates to semiconductor bus switches, and more particularly to isolated wells under bus-switch transistors.
Bus switches are often used in networking and other applications. For high-speed applications, bus switches using metal-oxide-semiconductor (MOS) technology should have both low on-resistance and capacitance to reduce the delay through the switch. The source and drain nodes of a bus-switch transistor connect to the busses while the gate is controlled by a bus-connecting enable signal.
The terminals of bus-switch transistors may be biased in a variety of ways to prevent latch-up or damage and to reduce sensitivity to glitches and other system or environmental factors. See for example “Parallel Micro-Relay Bus Switch for Computer Network Communication with Reduced Crosstalk and Low On-Resistance using Charge Pumps”, U.S. Pat. No. 5,808,502, and “Bus Switch Having Both P- and N-Channel Transistors for Constant Impedance Using Isolation Circuit for Live-Insertion when Powered Down”, U.S. Pat. No. 6,034,553. Also see U.S. Pat. No. 6,052,019 for “Undershoot-Isolating MOS Bus Switch”, “Bi-Directional Undershoot-Isolating Bus Switch with Directional Control”, U.S. Pat. No. 6,559,703, and “Live-Insertion PMOS Biasing Circuit for NMOS Bus Switch”, U.S. Pat. No. 6,608,517.
FIG. 1 shows a prior-art bus switch. Bus-switch transistor 10 can isolate bus A from bus B or can connect them together. The drain of bus-switch transistor 10 is connected to terminal A, while the source is connected to terminal B. Terminals A, B are typically input-output (I/O) pads of a semiconductor chip that contains one or more bus-switches. Drains and sources are terms that are interchangeable, depending on the applied biases of A, B.
An enable signal EN is applied to or generated by the chip, and is buffered by inverters 16, 18 to drive gate-enable signal GEN. Signal GEN is applied to the gate of bus-switch transistor 10. When EN is high, bus-switch transistor 10 turns on, connecting A and B. When EN is low, bus-switch transistor 10 turns off, isolating A from B.
As new electronic systems operate at higher and higher speeds, such as the Giga-hertz (GHz) range, such bus-switch transistors must also operate at the higher speeds. Capacitances need to be charged and discharged at the higher GHz rates. When capacitances are relatively large, such charging and discharging can limit the frequency of operation of the device.
Since terminals A, B are connected to external pins of the semiconductor chip housing bus-switch transistor 10, larger than minimum-size geometries are needed as protection against electro-static-discharges (ESD) to prevent damage to the device. The source and drain regions of bus-switch transistor 10 are usually enlarged to provide additional protection against ESD damage. This increased source/drain size leads to larger parasitic capacitances in bus-switch transistor 10.
For example, drain-to-well capacitor 14 is formed between the N+ source of bus-switch transistor 10 and the P-well or p-type substrate under the drain. The P-well is often grounded, so as the drain voltage changes as the external signal on A changes, drain-to-well capacitor 14 must be charged and discharged. When the switch is on, source-to-well capacitor 12 must also be charged.
FIG. 2 is a cross-section of a bus-switch transistor. Bus-switch transistor 10 is formed in P-well 17, which is biased to ground by a P+ tap. The N+ drain of bus-switch transistor 10 is connected to external bus signal A while the N+ source is connected to external signal B. The gate of bus-switch transistor 10 is driven by gate-enable signal GEN. The n-type substrate 94 is connected to power (Vcc) by N+ tap 92.
Drain-to-well capacitor 14 (FIG. 1) is formed between the N+ drain (connected to signal A) of bus-switch transistor 10 and grounded P-well 17 under the drain. Source-to-well capacitor 12 is formed between the N+ source (connected to signal B) of bus-switch transistor 10 and grounded P-well 17 under the source. A large size for the MOS transistors is needed for low on-resistance with high performance switches. At very, very high frequencies these capacitances can limit operation.
The parasitic capacitances of drain-to-well capacitor 14 and source-to-well capacitor 12 increase the input capacitance measured at terminals A, B since larger-than-minimum size sources and drains are needed for ESD protection. This increased input capacitance is undesirable since it can limit higher-speed operation of bus-switch transistor 10.
What is desired is a bus switch with low on-resistance and reduced input capacitance. A bus switch with reduced source/drain capacitance is desirable to allow operation at higher frequencies, such as in the GHz range.